Episode 00 - What HELUT Actually Is: Circuits You Can Search, and Where It Loses

Description:
A direct answer, not a pitch. Yosys turns Verilog into a netlist of lookup tables and flip-flops; HELUT evaluates that netlist as tensors on Apple silicon. That buys three operations an event-driven simulator does not have: the truth tables become continuous so they can be searched and then re-proved by Yosys and SAT, the same representation runs on encrypted data, and many independent instances ride in one submission. The episode opens on a live run where the carry logic is deleted from a two-bit adder, rediscovered by search, re-synthesized by Yosys, and proven equivalent to behavioural addition over the entire input space, with a corrupted value collapsing the proof. Then it states the losses without cushioning. On matched end-to-end work HELUT measured 8.544 ms against 7.422 ms for 16-worker Verilator at B=65,536: 15.1 percent slower, with no paired crossover through that width, and roughly four orders of magnitude behind at a single instance. On simplification it ties rather than wins: the discovered and hand-designed circuits map identically under one abc -lut 6 recipe, 0 wins, 18 ties, 0 losses. The encrypted path costs hundreds of milliseconds per gate and native-dimension processor checks still fail. No discrete-GPU comparison exists, so no cross-architecture claim is made; unified memory is presented as why host-orchestrated GPU search is practical on hardware you can buy, not as a measured win. What is proven: 65,536 distinct lanes with 589,824 output bits checked and zero mismatches, and one flip-flop repair proven by induction. Epoch C69. Site: https://helut.digitaldefiance.org · Source: https://github.com/Digital-Defiance/HELUT